Who we are

Kinara is a Bay Area-based venture backed company. Our architecture is based on research done at Stanford University by Rehan Hameed and Wajahat Qadeer under the guidance of legendary Prof. Mark Horowitz (http://www-vlsi.stanford.edu/~horowitz/) and Prof. Christos Kozyrakis http://csl.stanford.edu/~christos/).

What we do

Our game-changing AI solutions revolutionize what people and businesses can achieve. Ara inference processors combined with our SDK deliver unrivaled deep learning performance at the edge to accelerate and optimize real-time decision making where every millisecond is critical, and power efficiency is a must. Kinara solutions embed high-performance AI into edge devices to create a smarter, safer, and more enjoyable world. Edge AI is on the brink of a boom, and Kinara is looking forward to playing a significant role in it.

About the Role

We are seeking a talented Implementation Engineer to join our dynamic team. The successful candidate will be responsible for leading and executing Synthesis and STA for complex AI SOC with multi-mode and multi power domain design, ensuring the quality and reliability of our products.

This is what you are responsible for

• Synthesis and STA (static timing analysis).

• Ability to optimize designs for best in class in low power and high performance with logically equivalent RTL.

• Professional experience with ECO implementation, both functional and timing closure.

• Experience with multi-clock, multi-power domain designs and multi-mode timing constraints.

• Familiarity with DFT insertion.

• Familiarity with simulation, debugging tools, and working closely with Design teams.

• Ability to collaborate with different functional teams like RTL Design, DFT and Physical design.

• Showcase your deep understanding of the following physical design concepts/constraints: floor-planning, placement, congestion, and setup/hold timing closure.

Necessary Qualifications

• Bachelor’s or Master’s degree in Electronics, Computer Science Engineering, or a related field

• Minimum of 5 to 7 years of experience in Implementation flows/ Synthesis and STA.

• Experience with Cadence, Synopsys and Mentor tools

• Experience with Verilog and VHDL.

• Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks (UPF/CPF/CLP)

• Formal verification for RTL 2 gates and gates2gates

• Conformal ECO for doing complex functional ECOs.

• Low power synthesis on smaller blocks and subsystems using DC/Genus

• Physical Aware synthesis

• Writing Timing Constraints sub-blocks and Top level.

• Flow Automation and Scripting using TCL and Python or Perl.

Work culture

We at Kinara have an environment that fosters innovation. Our team has technology experts who understand the big picture and mentors who coach passionate professionals to work on the most exciting challenges. We share responsibilities in everything we do, where every point of view is valued. Join us!

Now tell us your story. We are looking forward to reviewing your application.

Make your mark!

Who we are

Kinara is a Bay Area-based venture backed company. Our architecture is based on research done at Stanford University by Rehan Hameed and Wajahat Qadeer under the guidance of legendary Prof. Mark Horowitz (http://www-vlsi.stanford.edu/~horowitz/) and Prof. Christos Kozyrakis (http://csl.stanford.edu/~christos/).

What we do

Our game-changing AI solutions revolutionize what people and businesses can achieve. Ara inference processors combined with our SDK deliver unrivaled deep learning performance at the edge to accelerate and optimize real-time decision making where every millisecond is critical, and power efficiency is a must. Kinara solutions embed high-performance AI into edge devices to create a smarter, safer, and more enjoyable world. Edge AI is on the brink of a boom, and Kinara is looking forward to playing a significant role in it.

About the Role

We are seeking a highly skilled and experienced Hardware Architect to join our dynamic team. The ideal
candidate will have a strong background in hardware architecture, particularly in writing architectural models and
conducting performance and power analysis of chips. In addition to collaborating closely with our hardware team, the
successful candidate will also work with our software department, which focuses on compilers, runtime software, and
kernel software, to ensure cohesive and efficient chip design and functionality.

This is what you are responsible for

Architecture Modeling:

• Develop architecture models for AI chips.

• Collaborate with cross-functional teams to ensure models accurately reflect design specifications and requirements.

• Utilize industry-standard tools and methodologies for architecture modeling.

Performance Analysis:

• Conduct in-depth performance analysis to identify and resolve bottlenecks in AI chip designs.

• Use simulation and analytical methods to predict and enhance chip performance.

• Work with software teams to validate performance models with real-world applications and workloads.

Power Analysis:

• Perform detailed power analysis to ensure AI chips meet stringent power consumption targets.

Necessary Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field

• Minimum of 8 years of experience in hardware architecture/design of silicon chips

• Strong understanding of computer architecture principles and AI chip design.

• Proficiency in C/C++/Verilog.

Preferred Qualifications:

• Excellent analytical and problem-solving skills.

• Strong communication and teamwork abilities.

• Ability to work in a fast-paced, collaborative environment.

• Detail-oriented with a focus on delivering high-quality results.

Work culture

We at Kinara have an environment that fosters innovation. Our team has technology experts who understand the big picture and mentors who coach passionate professionals to work on the most exciting challenges. We share responsibilities in everything we do, where every point of view is valued. Join us!

Now tell us your story. We are looking forward to reviewing your application.

Make your mark!

Embedded Firmware Developer

Who we are

Kinara is a Bay Area-based venture backed company. Our architecture is based on research done at Stanford
University by Rehan Hameed and Wajahat Qadeer under the guidance of legendary Prof. Mark Horowitz
(http://www-vlsi.stanford.edu/~horowitz/) and Prof. Christos Kozyrakis (http://csl.stanford.edu/~christos/).

What we do

Our game-changing AI solutions revolutionize what people and businesses can achieve. Ara inference processors
combined with our SDK deliver unrivaled deep learning performance at the edge to accelerate and optimize
real-time decision making where every millisecond is critical, and power efficiency is a must. Kinara solutions
embed high-performance AI into edge devices to create a smarter, safer, and more enjoyable world. Edge AI is on
the brink of a boom, and Kinara is looking forward to playing a significant role in it.

About the Role

We are seeking a talented embedded firmware developers to join our dynamic team. The successful candidate will be responsible for leading and executing verification efforts for complex ASIC designs, ensuring the quality and reliability of our products.

This is what you are responsible for

• Design, implement, and test firmware for embedded systems used in AI chips
• Optimize firmware for performance and power consumption to meet stringent AI application requirements.
• Work closely with hardware engineers to ensure seamless integration of firmware with hardware components.
• Diagnose and resolve firmware issues, ensuring robustness and reliability of the embedded systems.
• Collaborate with cross-functional teams including software developers, hardware engineers, and QA testers to deliver high-quality products.
• Create and maintain comprehensive documentation for firmware designs, implementations, and debugging procedures.

Necessary Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• Minimum of 3 years of experience in embedded firmware development.
• Proficiency in programming languages such as C and C++.
• Experience with embedded systems and microcontroller programming.
• Familiarity with real-time operating systems (RTOS) and embedded Linux.
• Knowledge of hardware interfaces and communication protocols (e.g., I2C, SPI, UART, CAN).
• Experience with debugging tools and techniques, such as JTAG, oscilloscopes, and logic analyzers.

Preferred Qualifications:

• Experience in developing firmware for AI or machine learning applications.
• Familiarity with AI chip architectures and performance optimization techniques.
• Knowledge of version control systems, such as Git.
• Experience with scripting languages like Python for test automation and data analysis.

Work culture

We at Kinara have an environment that fosters innovation. Our team has technology experts who understand the big picture and mentors who coach passionate professionals to work on the most exciting challenges. We share responsibilities in everything we do, where every point of view is valued. Join us!

Now tell us your story. We are looking forward to reviewing your application.

Make your mark!

Junior ASIC Verification Engineer

Who we are

Kinara is a Bay Area-based venture backed company. Our architecture is based on research done at Stanford
University by Rehan Hameed and Wajahat Qadeer under the guidance of legendary Prof. Mark Horowitz
(http://www-vlsi.stanford.edu/~horowitz/) and Prof. Christos Kozyrakis (http://csl.stanford.edu/~christos/).

What we do

Our game-changing AI solutions revolutionize what people and businesses can achieve. Ara inference processors
combined with our SDK deliver unrivaled deep learning performance at the edge to accelerate and optimize
real-time decision making where every millisecond is critical, and power efficiency is a must. Kinara solutions
embed high-performance AI into edge devices to create a smarter, safer, and more enjoyable world. Edge AI is on
the brink of a boom, and Kinara is looking forward to playing a significant role in it.

About the Role

We are seeking a talented junior ASIC Verification Engineer to join our dynamic team. The successful candidate will be responsible for leading and executing verification efforts for complex ASIC designs, ensuring the quality and reliability of our products.

This is what you are responsible for

• Develop and maintain verification plans, testbenches, and test cases for ASIC designs.
• Design and implement SystemVerilog/UVM-based verification environments.
• Create and execute test cases to verify functionality, performance, and compliance with specifications.
• Write testplans, testcases at unit or SOC level.

Necessary Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• expertise in SystemVerilog, C, C++ languages.
• Experience with verification tools such as VCS, QuestaSim, or similar is helpful.
• Excellent problem-solving and debugging skills.
• Strong communication and teamwork abilities.

Preferred Qualifications:

• Experience with scripting languages such as Python or Perl .
• Programming languages such as C,C++.
• Knowledge of industry standards and protocols (e.g., AXI, AHB, etc).
• Familiarity with formal verification techniques.

Work culture

We at Kinara have an environment that fosters innovation. Our team has technology experts who understand the big picture and mentors who coach passionate professionals to work on the most exciting challenges. We share responsibilities in everything we do, where every point of view is valued. Join us!

Now tell us your story. We are looking forward to reviewing your application.

Make your mark!

Senior Verification Engineer(8+ years of experience in verification)

Who we are

Kinara is a Bay Area-based venture backed company. Our architecture is based on research done at Stanford
University by Rehan Hameed and Wajahat Qadeer under the guidance of legendary Prof. Mark Horowitz
(http://www-vlsi.stanford.edu/~horowitz/) and Prof. Christos Kozyrakis (http://csl.stanford.edu/~christos/).

What we do

Our game-changing AI solutions revolutionize what people and businesses can achieve. Ara inference processors
combined with our SDK deliver unrivaled deep learning performance at the edge to accelerate and optimize
real-time decision making where every millisecond is critical, and power efficiency is a must. Kinara solutions
embed high-performance AI into edge devices to create a smarter, safer, and more enjoyable world. Edge AI is on
the brink of a boom, and Kinara is looking forward to playing a significant role in it.

About the Role

We are seeking a talented Senior ASIC Verification Engineer to join our dynamic team. The successful candidate will be responsible for leading and executing verification efforts for complex ASIC designs, ensuring the quality and reliability of our products.

This is what you are responsible for

• Develop and maintain verification plans, testbenches, and test cases for ASIC designs.
• Collaborate with design and architecture teams to understand design specifications and requirements.
• Design and implement SystemVerilog/UVM-based verification environments.
• Create and execute test cases to verify functionality, performance, and compliance with specifications.
• Debug failures and drive issues to closure, working closely with cross-functional teams.
• Mentor junior team members and provide technical guidance.
• Contribute to the continuous improvement of verification methodologies and best practices.
• Create and maintain verification environments for SOCs.

Necessary Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• >8 years of experience in ASIC verification, preferably in a senior or lead role.
• Strong expertise in SystemVerilog, UVM, OOP concepts and verification methodologies.
• Experience with verification tools such as VCS, QuestaSim, or similar.
• Proven track record of successfully delivering complex ASIC verification projects.
• Excellent problem-solving and debugging skills.
• Strong communication and teamwork abilities.

Preferred Qualifications:

• Experience with scripting languages such as Python or Perl.
• Knowledge of industry standards and protocols (e.g., PCIe, DDR, USB, Ethernet).
• Knowledge on the on chip interconnects, memory and processor subsystems.
• Familiarity with formal verification techniques.

Work culture

We at Kinara have an environment that fosters innovation. Our team has technology experts who understand the big picture and mentors who coach passionate professionals to work on the most exciting challenges. We share responsibilities in everything we do, where every point of view is valued. Join us! Now tell us your story.

We are looking forward to reviewing your application.

Make your mark!

VLSI Design Engineer

Who we are

Kinara is a Bay Area-based venture backed company. Our architecture is based on research done at Stanford
University by Rehan Hameed and Wajahat Qadeer under the guidance of legendary Prof. Mark Horowitz
(http://www-vlsi.stanford.edu/~horowitz/) and Prof. Christos Kozyrakis (http://csl.stanford.edu/~christos/).

What we do

Our game-changing AI solutions revolutionize what people and businesses can achieve. Ara inference processors
combined with our SDK deliver unrivaled deep learning performance at the edge to accelerate and optimize
real-time decision making where every millisecond is critical, and power efficiency is a must. Kinara solutions
embed high-performance AI into edge devices to create a smarter, safer, and more enjoyable world. Edge AI is on
the brink of a boom, and Kinara is looking forward to playing a significant role in it.

About the Role

Kinara focuses on edge AI technology, committed to pushing the boundaries of what’s possible in machine learning and artificial intelligence. We develop state-of-the-art AI processors, on-chip high speed interconnects that deliver unmatched performance, power efficiency, and scalability to meet the demands of modern AI applications. We also work on high speed interfaces like DDR, PCIE, USB etc. We are seeking a highly skilled and motivated VLSI Design Engineer to join our dynamic team. The ideal candidate will have a strong background in VLSI design, IP design, IP integration into SOC, Design Debug skills, synthesis, LEC, timing clean up, lint/CDC/CLP/UPF .This role involves working on cutting-edge semiconductor projects and requires a combination of technical expertise, problem-solving skills, and the ability to work collaboratively within a team environment.

This is what you are responsible for

• Define micro-architecture and write detailed design specifications.
• Develop RTL code based on system-level specifications using Verilog, VHDL, or SystemVerilog.
• Implement complex digital functions and algorithms in RTL.
• Create and execute detailed test plans to verify RTL designs.
• Optimize designs for power, performance, and area (PPA) constraints.
• Perform simulation and debugging to ensure design correctness.
• Work with verification engineers to develop test benches and validate RTL against specifications.
• Strong understanding of digital design principles and concepts.
• Proficiency in writing and debugging RTL code.
• Experience with synthesis, static timing analysis, and linting tools.
• Familiarity with scripting languages such as Python, Perl, or TCL for automation.
• Experience in any of processor subsystem design, interconnect design, high speed IO interface design.

Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of experience in RTL design and verification.
• Proven experience with digital logic design using Verilog, VHDL, or SystemVerilog.
• Experience with simulation tools such as VCS, QuestaSim, or similar.
• Hands-on experience with RTL design tools (e.g., Synopsys Design Compiler, Cadence Genus).

Work culture

We at Kinara have an environment that fosters innovation. Our team has technology experts who understand the big picture and mentors who coach passionate professionals to work on the most exciting challenges. We share responsibilities in everything we do, where every point of view is valued. Join us! Now tell us your story.

We are looking forward to reviewing your application.

Make your mark!

Who we are

Kinara is a Bay Area-based venture backed company. Our architecture is based on research done at Stanford University by Rehan Hameed and Wajahat Qadeer under the guidance of legendary Prof. Mark Horowitz (http://www-vlsi.stanford.edu/~horowitz/) and Prof. Christos Kozyrakis (http://csl.stanford.edu/~christos/).

What we do

Our game-changing AI solutions revolutionize what people and businesses can achieve. Ara inference processors combined with our SDK deliver unrivaled deep learning performance at the edge to accelerate and optimize real-time decision making where every millisecond is critical, and power efficiency is a must. Kinara solutions embed high-performance AI into edge devices to create a smarter, safer, and more enjoyable world. Edge AI is on the brink of a boom, and Kinara is looking forward to playing a significant role in it.

This is what you are responsible for

• Physical Design of complex data path and control blocks
• Develop new techniques and flows to rapidly prototype hardware blocks
• Develop flows that allow for detailed power estimation
• Work with design team to understand placement and recommend implementation options
• Interact and engage with external teams to drive as well as deliver subsystems leading to chip tapeout

Preferred qualifications

• BTech/MTech EE/CS with 8+ Years of Physical Design experience.
• Extensive knowledge of Automated synthesis, Technology mapping, Place-and-Route and Layout techniques
• Physical verification and quality checks like LVS, DRC, IR drop
• Clock tree synthesis, Power mesh design, Signal integrity.
• Latest foundry nodes up to 7nm
• Hands on experience with Synthesis, Automatics Place-and-route, Full Chip STA, IO Planning, Full Chip Floorplan, Power Mesh creation, Bump Planning, RDL Routing, Low power design flows
• Strong understanding of advanced digital design architectures and clocking structures to help manage timing and physical design constraints
• Ability to work with designers to analyse and explore physical implementation options for complex designs.
• Basic knowledge of DFT techniques and implications on Physical design
• Desired tool familiarity
• Industry standard PnR, Synthesis etc tools, TCL Scripting
• Strong communication skills and good team player

Work culture

We at Kinara have an environment that fosters innovation. Our team has technology experts who understand the big
picture and mentors who coach passionate professionals to work on the most exciting challenges. We share
responsibilities in everything we do, where every point of view is valued. Join us!

Now tell us your story. We are looking forward to reviewing your application.

Make your mark!

Who we are

Kinara is a Bay Area-based venture backed company. Our architecture is based on research done at Stanford University by Rehan Hameed and Wajahat Qadeer under the guidance of legendary Prof. Mark Horowitz (http://www-vlsi.stanford.edu/~horowitz/) and Prof. Christos Kozyrakis (http://csl.stanford.edu/~christos/).

What we do

Our game-changing AI solutions revolutionize what people and businesses can achieve. Ara inference processors combined with our SDK deliver unrivaled deep learning performance at the edge to accelerate and optimize real-time decision making where every millisecond is critical, and power efficiency is a must. Kinara solutions embed high-performance AI into edge devices to create a smarter, safer, and more enjoyable world. Edge AI is on the brink of a boom, and Kinara is looking forward to playing a significant role in it.

This is what you are responsible for

• Develop verification environments for modules, subsystems, top level and FPGA
• Build models, checkers and random test frameworks using SystemVerilog and UVM
• Participate in Low power analysis (UPF), power estimation, C modeling
• Perform lint, CDC, code coverage, functional coverage
• Formal verification of modules using SVA assertions

Necessary qualifications

• Experience in verifying complex subsystems and ASICs
• Experience with building scalable verification environments from scratch
• Proficient at Verilog, UVM, EDA tools, scripting, automation, build, regression systems etc.
• Exposure to FPGA emulation platforms, silicon bringup, board debug
• BTech/MTech in EE/CS with any level of experience