Who we are

Kinara is a Bay Area-based venture backed company. Our architecture is based on research done at Stanford University by Rehan Hameed and Wajahat Qadeer under the guidance of legendary Prof. Mark Horowitz (http://www.vlsi.stanford.edu/~horowitz/) and Prof. Christos Kozyrakis (http://csl.stanford.edu/~christos/).

What we do

• Hot startup delivering on Generative AI Semiconductor play for the edge
• Patented technology developed by founders during Ph.D at Stanford
• Best in-class Silicon performance, power, Only Edge AI company shipping in volume
• Peerless software tool suite that’s a game changer for the company
• Well funded, Marquee (GAFA) customers including top e-tailer and Tier 1 PC OEM
• Two generations of Silicon shipping in volume, mature software stack
• Well capitalized, Series B led by Tiger Global, TSMC, Western Digital, Stanford, Catchlight

Job Summary

We are seeking an experienced Hardware Architect with strong expertise in SOC-architecture, Micro-architecture design, RTL coding and system-level performance/power analysis. The ideal candidate will have a track record of owning complex blocks or subsystems from concept through silicon, balancing performance, power, and area (PPA), and working closely with software, asic-design, asic-verification, asic-physicaldesign teams. it requires deep architectural insight and hands-on implementation understanding to help guide design trade-offs and drive the next generation of AI inference accelerators.

Key Responsibilities

Architecture & Micro-Architecture

• Define product feature and capabilities and own the architecture for compute, memory, interconnect & high-speed interface subsystems in the AI inference chip.
• Collaborate with software to co-optimize hardware features for AI workloads.
• Collaborate with RTL designers to identify and complex technical issues/risks. Review and guide RTL implementation, ensuring consistency with architectural intent and timing/power goals
• Collaborate with Physical-design teams for Area/Floorplan refinment, Timing targets etc.
• Define and document interface specifications, control/status logic, and pipeline structures.
• Lead PPA analysis and trade-off discussions across RTL and architecture.

Modelling & Analysis

• Develop and maintain high-level architecture and performance models.
• Use simulation and architectural models to guide RTL-level improvements.
• Validate model predictions against RTL or emulation results and refine accordingly.

Necessary Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of experience in SOC design, SOC architecture, RTL design, micro-architecture.
• Strong understanding of computer architecture, memory hierarchies, SoC interconnects, and AI/ML compute architectures.
• Proven experience optimizing for performance, power, and area.
• Hands-on expertise in Verilog/SystemVerilog, C/C++, and scripting (Python/Tcl/Perl)

Preferred Qualifications:

• Experience with AI accelerators, DSPs, or high-performance CPUs/GPUs.
• Familiarity with performance modeling frameworks (e.g., Python/C++ based).
• Exposure to EDA tools, power/performance analysis, and hardware-software co-design.
• Strong analytical skills and a collaborative mindset.

Work culture

We at Kinara have an environment that fosters innovation. Our team has technology experts who understand the big picture and mentors who coach passionate professionals to work on the most exciting challenges. We share responsibilities in everything we do, where every point of view is valued. Join us!

Now tell us your story. We are looking forward to reviewing your application.

Make your mark!